1. Field of the Invention
The present invention relates generally to flip chip integrated circuits, and more particularly, to flip chip type solder joints capable of carrying greater currents at lower current densities.
2. Description of the Relevant Art
Flip chip surface mount technology is well known in the semiconductor industry for simplifying the packaging and interconnection of integrated circuits. Typically, a series of circular (as viewed from above, or semi-spherical in three dimensions) solder bumps are formed upon the upper surface of an integrated circuit or other substrate in electrical contact with active or passive devices formed upon such substrate. Such solder bumps are then aligned with pads formed upon a second substrate to which the first substrate is to be mounted. The use of solder bumps to interconnect such flip chip integrated circuits to underlying support substrates is disclosed, for example, within U.S. Pat. No. 5,261,593 to Casson, et al.; within U.S. Pat. No. 5,220,200 to Blanton; within U.S. Pat. No. 5,547,740 to Higdon, et al.; and within U.S. Pat. No. 5,564,617 to Degani,et al.
However, the need for conducting relatively high currents, particularly power and ground interconnections, through such solder bumps in high power applications poses a problem relating to solder and UBM (Under Bump Metal) electromigration, which can in turn present functional and reliability issues during the device operating life. Electromigration results in a separation of the elements of the solder joint and/or preferential movement of the UBM intermetallics through the solder joint. Typical flip chip solder bumps can experience early failures due to electromigration when exposed to a high current density at a given junction temperature.
When a current is applied through a solder interconnect, the potential exists for a segregation of the elements due to electromigration. An example of a 63Sn/37Pb flip chip solder bump in which electromigration has occurred is shown in the cross-sectional enlarged photograph of FIG. 1; incidentally, the gap present between the silicon chip 20 and layer 22 labeled “Sn” is simply material that fell out during the cross sectioning process. In FIG. 1, the direction of the electron flow is from the silicon chip 20 to the copper pad 24 on the printed circuit board substrate 26. Typically, the worst electromigration is seen with this direction of electron flow, since the via on the silicon chip is smaller than the printed circuit board solder pad, and hence, the current density is highest at the silicon chip via It may be seen in FIG. 1 that the Pb component (i.e., the darker-colored material 23) has completely migrated from a uniform distribution to a localized area on the top of the printed circuit board pad.
The critical factors for electromigration of flip chip solder bumps are (1) the solder bump temperature; (2) the via cross-sectional area; and (3) the current per bump. It is known that Pb migrates preferentially at temperatures greater than 125° C. It has also been observed that Sn migrates preferentially at near room temperature.
One method of reducing current density in flip chip circuits is to use two or more solder bumps to form parallel current-conducting paths. However, in a given flip chip design, there is typically a limited amount of area in which to position the solder bumps, even in a full-array type design. There are limits as to how close together such solder bumps can be arranged to avoid the violation of processing design rules, and the use of two or more solder bumps to form parallel connections is not a very effective use of the limited area available in which to make all necessary electrical interconnections. Another method of handling large currents is to use wire bonds instead of solder bumps, but this approach is not cost effective; it tends to increase the size of the integrated circuit die, and may not meet the inductance requirements of the application.
Accordingly, it is an object of the present invention to provide a relatively compact solder joint configuration which is compatible with conventional flip chip processing techniques and which effectively increases the cross-sectional area of the solder joint, thereby reducing current density, providing higher current-handling capacity, and improving device operating life, as compared with conventional flip chip solder bumps.
It is another object of the present invention to provide such a solder joint configuration that can be formed upon the same substrate as conventional solder bumps.
Still another object of the present invention is to provide such a solder joint configuration that has a relatively uniform height.
Yet another object of the present invention is to provide such a solder joint configuration wherein the height thereof is approximately equal to the height of a conventional solder bump formed upon the same substrate.
A further object of the present invention is to provide a method for selecting the dimensions of such a solder joint configuration in order to minimize variations in the height of such solder joint configuration.
These and other objects of the present invention will become more apparent to those skilled in the art as the description thereof proceeds.